SpaceX is hiring a

Senior Physical Design Engineer

Redmond, United States

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.



  • You will be responsible for implementation of all phases of ASIC/SOC design (RTL2GDSII flow).
  • RTL synthesis and APR using industry standard tools.
  • Driving power, timing, and layout convergence of multiple designs.
  • Digital Back-end physical design.
  • Debugging post-silicon circuits and systems to root-cause logic and circuit issues.


  • Bachelor of Science Degree in Computer Engineer, Electrical Engineering or equivalent.
  • 10+ years of work experience
  • Previous work experience with DFT Scan Insertion and ATPG vector generation.
  • Previous work experience with Synthesis tools, Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.


  • Work with physical design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
  • Hands on experience in Synthesis, physical design, backend timing and large chip integration.
  • Experience with DFT Scan Insertion and ATPG vector generation.
  • Familiarity with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration (Digital / RF / Mixed Signal).
  • Familiarity with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
  • Familiarity with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
  • Must have experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
  • Experience with large SoC designs (>20M gates) utilizing state of the art deep sub-micron technologies.
  • Detailed understanding of database management issues.
  • Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
  • Work with external ASIC Vendors to drive SOC execution forward.
  • Be focal point for place and route drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.
  • Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
  • Demonstrate the ability to work in a dynamic environment that includes working with changing needs and requirements.
  • Team-player, can-do attitude, works well in a group environment while still being able to contribute on an individual basis, enjoys being challenged, learn new skills.


  • Must be able to work all shifts and available for overtime and weekends as needed. Some travelling will be necessary.


  • To conform to U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.

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