Toronto, Canada

Astera Labs is a global leader delivering semiconductor-based connectivity solutions purpose-built to unleash the full potential of intelligent data infrastructure at cloud-scale. Our class-defining first-to-market products based on PCIe, CXL, and Ethernet technologies deliver critical connectivity for high-value artificial intelligence and machine learning applications. Our focus on customer-driven product definition and commitment to design solutions in the cloud, for the cloud, results in breakthrough execution and scale for our customers. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.

Basic qualifications:

Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!

Required experience:

Hands-on and thorough knowledge of synthesis, place and route, timing, extraction and other backend tools and methodologies for technologies 16nm or less.
Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
Experience with Cadence and/or Synopsys physical design tools/flows.
Familiarity and working knowledge of System Verilog/Verilog.
Experience with DFT tools and techniques.
Experience in working with IP vendors for both RTL and hard-mac blocks.
Good scripting skills in python or Perl

Preferred experience:

Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
Familiarity with DFT test coverage and debug.
Familiarity with ECO methodologies and tools.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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Astera Labs is hiring a

Senior Physical Design Engineer