Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
Aeva is seeking a strong verification engineer to lead and verify the state-of-art DSP designs for new breeds of SoC for advanced perception applications utilizing 4-D Lidar. In this role, you will closely work with design and verification architects to define and develop verification environments for block, subsystem, and full-chip using constrained random verification techniques and verify complex DSP designs.
What you'll be doing:
- Lead the verification effort for state-of-art DSP design at block, subsystems, and full-chip level verification environments.
- Architect and build test benches, constrained random verification environments, reference models, and scoreboard using SystemVerilog and UVM methodologies
- Build self-checking environments using Matlab, C/C++ reference models, and DPI flow and verify DSP blocks against bit-accurate C-reference models
- Define and execute verification plan for IP, block, subsystem, and full-chip using SystemVerilog/UVM methodology
- Work in a dynamic and fast-paced startup environment and work closely with a team of passionate engineers to define the processes, methodology, and tools to verify complex DSP and SoCs.
- Identify and write functional coverage to improve test/stimulus quality
- Analyze Code, Functional, and test plan coverages to identify verification gaps and achieve 100% coverage closure
- Work with the different stakeholders and functional leads to ensure high-quality DSP design delivery on time
What you'll have:
- 10+ years of experience in the design, verification, and validation of complex IPs, SOCs
- 5+ years in architecting and building block and top-level test benches, reference models, scoreboards, and directed self-checking tests using SystemVerilog and UVM methodologies
- Experience in verifying DSP design is highly desirable Solid programming and debugging skills in SystemVerilog, UVM, C/C++, Perl/Python.
- Working experience and knowledge in AMBA AXI protocols, LPDDR, Ethernet, and high-speed serdes, etc.
- Proficient in debugging complex IP and SOC designs
- Ability to collaborate deeply with cross-functional leads and management teams
- Desire to learn & implement groundbreaking new processes and methodology for continuous verification improvement
Nice to haves:
- Developing and integrating C/C++ reference model in the simulation environment
- Experience in verifying ARM-based SOC using C/C++ and SV/UVM methodology
- Post-silicon bring-up and validation planning and execution
What's in it for you:
- Be part of a fast-paced and dynamic team
- Very competitive compensation and meaningful stock grants
- Exceptional beneﬁts: Medical, Dental, Vision, and more
- Unlimited PTO: We care about results, not punching time cards