Technologist, ASIC Development Engineering (ASIC Power Architect)

ASIC Power Architect - Job Description

We are seeking a highly skilled and experienced ASIC Power Architect to join our dynamic team responsible for SoC Architecture of next-generation of Flash Controllers.

As an ASIC Power Architect, you will be responsible for defining Multi Power Domain architectures in SoC, with a particular focus on Low-Power states.

The ideal candidate will have a deep understanding of SoC development flow, power management, and the ability to drive architecture convergence to deliver high-performance, low-power, and cost-effective solutions.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Power Analysis based on RTL/Netlist including early power estimation based on previous generation architectures
• Power Optimization techniques at various phases on Design & Development
• Defining Methodologies and Processes for next generation power aware design, development and implementation
• Working closely with and guiding PD implementation from Power optimization perspective
• Characterization process / data analysis with emphasis on Voltage scaling methodologies – SVS / DVFS / DVS and binning
• Leading complex activities while having multiple interfaces
• Collaborate with cross-functional teams to define and refine Power Architecture, ensuring alignment with industry standards and customer needs.
• Working closely with the Design, Verification, DFT and Physical Design teams while guiding them.
• Evaluate all aspects of the ASIC power management from requirements, through definition phase, Design, Verification and to Synthesis, Place and Route, Timing and Power optimizations.

SKILLS:

• Extensive experience in SoC architecture, Power Management and full ASIC flow.
• Solid understanding of Power Management techniques and Low-Power design principles.
• Physical Understanding on latest Process technologies N7 & N5
• Hands on in Silicon debug of complex power issues
• Proficiency in Low-Power standards like UPF/CPF.
• Working knowledge on UPF based RTL / PGPIN simulations.
• Proficiency in ASIC design tools, simulation methodologies, and hardware description languages (HDLs).
• Excellent analytical and problem-solving skills with a focus on power optimization.
• Strong communication skills and the ability to work effectively in cross-functional teams.

Minimum Qualifications:

• Bachelor/ Master degree in Electronics/VLSI/Micro-Electronics Engineering 
• At least 10 years of experience in ASIC Power architecture

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