R&D Physical Design Engineer
TLDR
Drive full-chip physical design, including floorplanning, placement, signoff (STA, DRC/LVS) and 7nm tapeout challenges within the ASIC flow.
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Job Description:
Physical Design Implementation: An ideal candidate having strong background in either the Physical Design which includes floor planning, placement, design closure, STA, and DRC & LVS skills.
Overall, candidates are expected to develop the most of above skills. Candidates who have the desire to seek the in-depth and broad technical challenge should apply.
It would be better if the candidate have the experience running full chip signoff tasks including PI, SI, PV and STA.
Requirements/Qualifications
- Candidates should have good understanding about ASIC design flow and solid VLSI background.
- Candidates should be able to handle block implementation/top level task independently.
- Tapeout experience in 7nm and blow process design.
- Candidate s should have strong communications and problem solving skills.
- Candidates with experience in any one of following knowledge are a plus
- DFT insertion
- Power/IVD analysis
- DRC/LVS
- STA
- Candidate is good at Perl/Tcl
Education/Certifications
Preferred Degree: 7+ years MS Preferred
Major: Microelectronics or related discipline
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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Avago Technologies develops industry-leading software solutions that power mainframe systems, which are crucial to the digital economy and support a significant portion of structured corporate data and enterprise applications. By partnering with Fortune 1000 companies, we ensure that their operations remain efficient and reliable while continually enhancing our capabilities in semiconductor manufacturing.