Design Verification Engineer
TLDR
Defines and implements verification methodology for next-gen ASIC, focusing on PCIe and 400G MAC verification.
Job Title: Design Verification Engineer
Location: Santa Clara, CA
Duration: 06 months (High Possibility of an extension)
Job Description:
Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key areas of our next generation ASIC:
1. PCIE verification background
2. 400G MAC verification background
All your information will be kept confidential according to EEO guidelines.
Insilico builds end-to-end specialized VLSI, Embedded Design, and Software services and solutions tailored for top semiconductor companies. By focusing on Compute and Connectivity, Insilico offers a diverse range of services from Spec-to-Silicon across various industries, including communication, automotive, and IoT, making it a significant player in the tech landscape.