Insilico
STA Engineer
TLDR
Address RTL timing and functional verification challenges using formal methods and industry toolchains to deliver robust silicon designs.
Job Profile: STA Engineer
Experience: 10+ Years
Duration: 12+ Months
Location: Sunnyvale, CA
- Basic Knowledge on RTL
- Synthesys ( able to understand and debug all the Warning and Error messages )
- Scan insertion.
- Handle on Functional eco ( with conformal tool and if the design change is minimum able to edit the netlist by looking at the RTL change with the help of RTL designer)
- Logical equivalence ( Formality/Conformal ); Need deep knowledge on debug
- Timing closure
- Understanding on constraints and able to give feedback to the RTL designer.
Tool experience: Synopsys DC, Formality, Primetime and Cadence conformal.
All your information will be kept confidential according to EEO guidelines.
Insilico builds end-to-end specialized VLSI, Embedded Design, and Software services and solutions tailored for top semiconductor companies. By focusing on Compute and Connectivity, Insilico offers a diverse range of services from Spec-to-Silicon across various industries, including communication, automotive, and IoT, making it a significant player in the tech landscape.